Typically, an output buffer will actively drive an output terminal either to a high voltage or to a low voltage state until data from a subsequent data cycle is available at the output buffer, at which time the output buffer will drive the output terminal with the new data. It is desirable that the output terminal be driven as quickly as possible to achieve the voltage level of the new data. Where the output terminal drives an external capacitive load, delay times are excessive especially in view of the speed of operation of the circuits generating the data to be applied to the output terminal. The rate at which the output load can be driven is generally difficult to increase by increasing the speed of the circuitry generating the data due to the capacitive and inductive nature of the load. Further, if the speed of operation of the circuit generating the data is increased, such operation causes increased noise levels on internal power supply lines.
A need has thus arisen for a circuit for actively driving the voltage of an output terminal to a mid-level voltage after old data is no longer needed and prior to the receipt by the output terminal of new data in order to reduce the voltage swing on the output terminal after the receipt of new data thereby reducing the delay time for the output terminal to reach the voltage level of the new data. A need has further arisen for a circuit for presetting the voltage of an output terminal in order to reduce the noise of the power supply during the time of output switching.